STRUCTURED REGULARIZATION MODELING FOR VIRTUAL METROLOGY IN SEMICONDUCTOR MANUFACTURING PROCESSES
DOI:
https://doi.org/10.23055/ijietap.2019.26.6.4985Keywords:
industrial engineering, quality management, manufacturing engineering, information technologyAbstract
Virtual metrology (VM) has been developed to economically perform wafer-to-wafer control, and has been used to estimate actual measurements from process data collected via sensors attached to corresponding equipment. Sensor data contains a large number of highly correlated and grouped features. Despite great potential of structured regularization models for addressing the group structure in sensor data, little effort has been made to examine their performance in terms of VM modeling. The main objective of this study is to propose use of structured regularization models for VM modeling and compare them with unstructured regularization models in terms of predictive accuracy, feature-selection accuracy, and stability. The effectiveness of unstructured regularization models was demonstrated through experiments with synthetic data as well as real data obtained during semiconductor manufacturing processes. Results of these experiments demonstrate that feature-selection accuracy and stability of structured regularization models were superior to those of corresponding unstructured regularization models.
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